Along the significant advancement of various information devices ranging from mobile terminals to high-capacity servers, further higher performance, i.e., high-degree of integration, high speed, and low power consumption are pursued also in elements such as memories and logics constituting those devices. In particular, the progress of semiconductor nonvolatile memories is striking, and a flash memory as a high-capacity file memory is increasingly prevailing while increasing momentum of overtaking a hard disk drive. On the other hand, in order to aim at development to a code storage or working memory and replace a NOR flash memory, a DRAM, and the like currently widely used, a FeRAM (Ferroelectric Random Access Memory), an MRAM (Magnetic Random Access Memory), a PCRAM (Phase-Change Random Access Memory), and the like are in the process of being developed. Some of them are already put into practical use.
Among those memories, the MRAM stores data depending on a magnetization direction of a magnetic body and thus enables rewrite at high speed and almost infinitely (1015 times or more). The MRAM is already used in the fields of industrial automation, aircraft, and the like. The MRAM is expected to be developed in a code storage or working memory in the future because of its high-speed operation and reliability.
In recent years, in contrast to magnetic storage of a horizontal magnetic type, a perpendicular magnetic type that is suitable for reduction in area of a memory cell has been proposed. Due to responsiveness of data access (write/read) and being a nonvolatile RAM, a demand for replacement of a DRAM is conceived, but it is indispensable to reduce the size of a memory cell that is comparable to the DRAM, that is, reduce a bit unit price.
The MRAM is similar to a DRAM in the structure as a semiconductor memory, and has such a shape that a capacitor portion in the DRAM is replaced with an MTJ (Magnetic Tunnel Junction) element.
In the structure of the MRAM already mass-produced, a transistor for selecting each MTJ, a bit line, a word line, an MTJ, and a data line are laminated on a substrate in the stated order from the bottom. In other words, the MTJ is disposed on the almost uppermost layer of the element, and the word line and the bit line are formed as memory connecting wires in laminated wiring between elements, which is a second-half step (Back End Of Line) of semiconductor manufacturing. In the structure, after the memory connecting wires are formed, an MTJ to be a memory element is laminated on those connecting wires, and data line is then formed.
Specifically, the structure in which components from an access transistor (field-effect transistor) to an MTJ are drawn to the vicinity of the uppermost layer of the metal wires and then connected is the mainstream. In this case, since the bit line and the word line are drawn to the MTJ, the resistance of the bit line and the word line becomes large, and thus a current for rewriting the memory content of the MTJ cannot be increased. This becomes a problem in terms of current control. As one of methods for solving this problem, an attempt to make a perpendicular-type access transistor is performed (see Patent Document 1).